The present invention relates to an operation mode setting circuit and, more particularly, to a circuit which sets an operation mode immediately after the power supply is turned on in a semiconductor integrated circuit.
A semiconductor integrated circuit generally has an integrated circuit dedicated to testing and includes a test mode different from a normal operation mode, in order to facilitate testing.
Since, however, the test mode is different from the normal operation mode, a user does not operate the semiconductor integrated circuit in this test mode. Therefore, if the test mode starts for some reason while the user is operating the semiconductor integrated circuit, this test mode is regarded as an operation error.
Accordingly, design of a semiconductor integrated circuit requires some “mechanism” which prevents switching to the test mode while a user is normally operating the semiconductor integrated circuit.
As an example of this “mechanism”, FIG. 5 shows the arrangement of a conventional circuit for setting an operation mode.
4-bit operation mode setting signals “mode bits 0 to 3” are input to four test mode input terminals IN101 to IN104 from a CPU or another external circuit (neither is shown). A normal operation mode and test mode are switched by the combination of these 4-bit signals.
FIG. 6 shows operation modes determined by the combination of the 4-bit operation mode setting signals.
In a normal operation mode, all mode bits 0 to 3 take the value of logic “0”. To enter any of test modes A to C, mode bit 3 takes the value of logic “1”. Each test mode is determined by the combination of logics “1” and “0” in remaining mode bits 0, 1, and 2.
Since a user is forced to fixedly use logic “0” in all mode bits 0 to 3, the semiconductor integrated circuit does not enter any test mode by mistake.
The operation of the conventional operation mode setting circuit will be described below with reference to FIG. 5.
Of mode bits 0 to 3 input to the input terminals IN101 to IN104, mode bits 0 and 3 remain the same, and mode bits 1 and 2 are inverted by inverters IV101 and IV102, respectively, and input to an AND circuit AD101. The output from the AND circuit AD101 is supplied to a latch circuit LC101. At a timing synchronized with a clock CLK supplied from a clock generator CG101, the latch circuit LC101 latches and outputs the output from the AND circuit AD101. This output is output from an output terminal OT101 to, e.g., a CPU (not shown).
If the output from the AND circuit AD101 is logic “1”, the operation mode is test mode A. If the output is logic “0”, the operation mode is any of the normal operation mode and test modes B to D. Note that in the following explanation, test mode A is used as the test mode, and a case in which it is necessary to distinguish between the normal operation mode and test mode A will be described.
The following is a reference which discloses a technique concerning the conventional operation mode setting circuit.
Japanese Patent Laid-Open No. 2001-273054
Unfortunately, the conventional operation mode setting circuit described above has the following problems.
Immediately after the power supply is turned on, the output level of the latch circuit LC101 is unstable, and the output is either logic “1” or “0”.
This is so because the clock CLK which is required to latch the data into the latch circuit LC101 is not generated immediately after the power supply is turned on.
The clock CLK is not generated until all circuits in the semiconductor integrated circuit become normally operable, i.e., until a quartz oscillator of the clock generator CG101 which generates the clock CLK becomes stably operable in the semiconductor integrated circuit after the power supply is turned on.
To eliminate this phenomenon which occurs immediately after the power supply is turned on, a power on clear circuit POC is added to force the output from the latch circuit to “0”.
FIG. 7 shows an example in which the power on clear circuit POC is added to the latch circuit LC101 shown in FIG. 5.
When the power supply is turned on, the power on clear circuit POC outputs a pulse while the power supply voltage rises. This pulse is supplied to a reset terminal R of the latch circuit LC101, and the output from the latch circuit LC101 is fixed to “0”.
Consequently, after the power supply is turned on, the semiconductor integrated circuit enters the normal operation mode, and does not switch to test mode A.
Even in this arrangement including the power on clear circuit POC as described above, however, it is sometimes impossible to eliminate the above-mentioned phenomenon in which the output from the latch circuit LC101 is unstable after the power supply is turned on. The reason will be explained below.
The power on clear circuit POC senses the rise of the power supply voltage, and generates one pulse accordingly. Therefore, the characteristics of the power on clear circuit POC are largely influenced by the rise time of the power supply voltage.
As shown in FIG. 8, a power on clear circuit generally has a capacitor C, resistor R, and switching transistor T. As shown in FIG. 9, after a power supply voltage VDD rises, the power on clear circuit generates a pulse POCP by discharging the capacitor C.
If the power supply voltage VDD rises slowly, the generated pulse POCP peaks at an insufficient height, so the output from the latch circuit LC101 cannot be reset in some cases.
Accordingly, the output from the latch circuit LC101 sometimes becomes logic “1” after the power supply is turned on. Once this output becomes “1”, this “1” output state cannot be reset unless the clock CLK is supplied to the clock terminal L.
As a consequence, the semiconductor integrated circuit enters test mode A. However, this is an operation error to the user, and increases the possibility of a defective operation in the user system.
To prevent this event, it is necessary to define a maximum value of the rise time of the power supply voltage to reliably execute this operation. In addition, the user must design the system board such that the rise time is equal to or smaller than this maximum value. This operation is cumbersome for the user, and increases the cost.